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PatternScan
A high-performance and visualization tool for pattern matching

PatternScan

PatternScan is used for pattern matching and is composed of two modules: Pattern Library and Pattern Match. The tool can easily handle pattern search tasks in ultra-large-scale layouts with a high-performance pattern matching engine. In addition, PatternScan can be used together with other tools in the DFMEXP platform to provide multiple automated solutions, such as process hotspot detection and optimization, design of layout physical verification at cell-level, and physical diagnostics and analysis.

High performance engine for pattern matching
With the self-developed high-performance algorithms, PatternScan achieves the industry-leading level in terms of pattern matching performance and supports pattern search tasks in ultra-large-scale layouts.
Efficient methods for creating and managing pattern libraries
PatternScan provides a GUI to create and manage pattern libraries, which enables users to create and manage rules to check complex patterns.
Powerful software ecosystem support
PatternScan can be used with other tools in the DFMEXP platform to provide multiple yield enhancement solutions in complex scenarios.

Benefits

    • Process hotspot search and optimization
    • Code-free layout physical verification
    • Design cell-level layout physical verification
    • Batch layout replacement and optimization
    • Diagnostics and yield analysis

Features

  • High performance engine for pattern matching
  • Efficient methods for creating and managing pattern libraries
  • Provide flexible definition of constraint rules and support customized fuzzy matching criteria
  • Support batch creation of pattern libraries
  • Combine GUI and script invocation and support automated batch execution of pattern matching tasks
  • Integrated with the Semitronix yield ecosystem to provide flexible yield solutions
Workflow
Case
Before tape-out, PatternScan is used for physical verification of the SRAM areas in the layout, which supplements design rule checks to prevent design errors in the SRAM regions.
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